Data conversion is a critical technology in many applications. Analog-to-digital converter (ADC) technology is progressing much slower (˜1.5 Bits in 9 years, see e.g. R. H. Walden, “Performance trend for analog-to-digital converters,” IEEE Comm. Magazine, February 1999 pp. 96-101) than digital signal processing (DSP) technology (which follows Moore's law). The main reasons for the slow advance are the bottlenecks of high-resolution/high-speed analog circuits. Many commercial analog-to-digital converters (ADCs) today use a Pipeline/Subranging (P/S) architecture (see FIG. 1) to combine two or more low-resolution, high-speed ADCs in order to achieve high-resolution while maintaining wideband operation.
Analog-to-digital conversion is a critical technology in many fields (communications, measurements, military/defence, medical equipment, etc.). Among others, it enables use of the advanced digital and computer technology in digital processing of signals. One example is SDR (Software Defined Radio) base station (BS) applications, were the analog-to-digital conversion is one of the enabling technologies. One identified analog-to-digital conversion bottleneck represents the difference between the required and achievable number of ADC bits for multicarrier/multi-standard BS. About 17 bits are needed, while the state of the art ADC commercial technology, (usually a P/S architecture) is only 14 bit (about 12 effective bits). In addition, ADCs are important for the new generations of Mobile/Handset, Asynchronized Digital Subscriber Line (ADSL) receivers (where 14 effective bits are required to reduce the distance limitation of ADSL) and other home and consumer applications. The fastest ADC architecture is the Flash architecture, but its resolution is limited to about 8 bits by the number of comparators used. Full Flash requires 256 comparators for 8 bit resolutions.
A popular prior art high-speed and high-resolution ADC architecture is the P/S architecture 100 shown in FIG. 1. Typically, an architecture 100 comprises an input sample and hold (S/H) circuit 102, a first stage 104, a digital correction and time alignment block 106, optional S/P additional stages 108 and a final low-resolution ADC 110, interconnected as shown. A typical stage 104 includes a low-resolution ADC 112, a high accuracy digital-to-analog converter (DAC) 114, a subtractor 116, and an optional second S/H unit 118, interconnected as shown.
In use, the voltage of an incoming time domain analog signal 111 is first sampled with S/H circuit 102 which must have the final accuracy of the converter, and then measured with low-resolution ADC 112. The voltage of the measured digital signal is reconstructed in the time domain with high DAC 114 into a reconstructed output voltage 128, which is input to subtractor 116. Subtractor 116 subtracts output voltage 128 from a low-resolution replica 130 of the sampled input voltage that goes through second, optional S/H 118, and creates an error voltage 132. Error voltage 132 is then amplified in a Gain unit 120 and measured with final low-resolution ADC 110. The process can be repeated with optional additional S/P stages 108 inserted between the “final” ADC and the first ADC stage.
The level of the error voltage is amplified to a required level at an output 140 of any additional or final ADC. Extra bits of low-resolution ADCs from all stages are used for digital correction using block 106.
A main disadvantage of this architecture is that it requires an accurate analog path that includes S/H units, subtractors and amplifiers. AU these components have to settle to the final accuracy of the voltage within the short sampling pulse period of the entire system. This requirement is a serious “analog” bottleneck in terms of both accuracy and maximum speed of the converter.
Other ADC architectures such as Folding/Interpolating are also used at higher sampling rates, but they do not provide the resolution of the S/P architectures. Use of parallel converters (time or frequency interleaving methods) increases the sampling rate, but comes at a cost of a linear increase in the number of converters in parallel. Moreover, in addition to increased cost and matching difficulties, these architectures do not improve the basic converter resolution and/or dynamic range (DR).
When a proper linear ADC with enough resolution/DR is not available (for a given sampling speed/bandwidth) or is beyond the state of the art, DR reduction techniques are sometimes proposed in order to reduce the DR of the strong signals (usually interfering signals) at the input to the lower resolution ADC to avoid saturation of the ADC. Examples are given in K. Huang, Q. S. Quek, S. N. A. Ahmed, B. Jin, and M. A. Kumar, “Techniques for reducing dynamic-range requirements for a software radio receiver”, Proceedings of Software Defined Radio Technical Conference 2002, November 2002; and K. Huang and Q. S. Quek, “Method for Dynamic Range Reduction in Wideband Receiver”, PCT/SG02/00196 filed 28, Aug. 2002, and references therein, specifically U.S. Pat. Nos. 6,195,537, 5,694,395 and 5,826,181.
In Huang's paper and patent applications, the wideband input signal from the receiver is split into two (first and second) signals with respective paths. The second signal is digitized and the filter of the communication channel frequency (which is assumed known) is used to suppress the desired signal in the second signal path. The resulting signal is used to suppress the strong interferers by subtracting them from the first signal.
The main disadvantage in Huang's method is that it operates only in a known communication channel and results in a relatively small improvement, which is also strongly dependent on the strong interferers characteristics. The main disadvantage of all prior art DR reduction methods and systems is that they do not provide linear analog to digital conversion over the entire input DR. Most of these methods and systems are also limited to specific applications.
There is therefore a widely recognized need for, and it would be highly advantageous to have, data converter methods and systems (or architectures) that do not require accurate analog circuits such as S/H, precision amplifiers and subtractors, yet provide higher final output resolution and conversion speed than existing state of the art methods and systems.
It would be also advantageous to have ADCs with an optional digital output in the frequency domain, which can be used for digital filtering, channelization, and spectrum analysis applications in areas such as communication, measurement and test equipment, medical equipment and military/defense systems.